Minimizing Power Dissipation in Scan Circuits During Test Application
نویسندگان
چکیده
Motivation for reducing power dissipation during test application is presented. A scheme for reducing power dissipation during test application, when scan test structure is used, is proposed. Algorithms required to exploit the proposed technique are discussed. Experimental results are presented. keywords: Power dissipation, Full Isolated Scan, Full Integrated Scan.
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